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humandude's avatar
humandude
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4 years ago
Solved

System Verilog Concatenation

If I have an 8-bit register and I concatenate an input bit to itself excluding the MSB, what does the output look like? My assumption is that the value gets bit-shifted to the left (i.e the MSB gets ...
  • ak6dn's avatar
    ak6dn
    4 years ago

    Yes, 100% correct. Same in Verilog or SystemVerilog.

VenT_Altera's avatar
VenT_Altera
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4 years ago

Hi,


I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Best Regards,

Ven Ting


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.