System Verilog Concatenation

Hi,

I have performed some compilation and simulation on the code in Modelsim. It verifies the discussion above. For the 2 bit-shifting to the right, zeros did fill in the upper two bits.

input [7:0] reg1;

input [1:0] input_bit;

output [7:0] out1, out2, out3, out4, out5;

output [8:0] out_shift;

//reg1 = 8'b10110010;

//input_bit = 1'b11;

assign out1 = {reg1 [6:0],input_bit [0]};

assign out2 = {reg1[7:0], input_bit};

assign out3 = {input_bit,reg1[7:0]};

assign out4 = {reg1, input_bit};

assign out5 = {input_bit,reg1};

assign out_shift = {input_bit[0], reg1}>>2;

Thanks.

Best Regards,

Ven Ting