Forum Discussion
humandude
New Contributor
New ContributorSystem Verilog Concatenation
If I have an 8-bit register and I concatenate an input bit to itself excluding the MSB, what does the output look like? My assumption is that the value gets bit-shifted to the left (i.e the MSB gets ...
Yes, 100% correct. Same in Verilog or SystemVerilog.
ak6dn
Regular Contributor
Regular ContributorYou are correct on that, my mistake. I checked a few tests in a couple different verilog simulators.
Whatever the bit width is inside the { } will be the result width, zero extended left/right as necessary.
The external shift { }<<N or { }>>N value 'N' will not change the width of the resultant expression.
Zeroes will be shifted in, or shifted bits truncated as necessary.
