System Verilog Concatenation

Both those examples are incorrect.

In the first, input_bit is still defined as a one bit register, so assigning 2'b11 to it actually results in a value of 1'b1.

So the result assigned to reg1 in the first case would be {8'b10110010,1'b1} truncated to the rightmost 8bits is 8'b01100101.

In the second case, the value {1'b1,8'b10110010} truncated to the rightmost 8bits is 8'b10110010.

When assigning a wider bitfield on the right hand side to a smaller width destination left hand side, the upper bits are truncated.
There is no implied shift, only truncation of the upper unused bits.
If you want a shift to occur, it must be explicit using the shift operator, like: {1'b1,8'b10110010}>>2 yields 7'b1101100.

I think you meant to define reg [1:0] input_bit , that would make more sense for your example.

Then:

reg [7:0] reg1 = 8'b10110010;
reg [1:0] input_bit = 2'b11;

reg1 <= {reg1[7:0], input_bit};  // reg1 <= {8'b10110010,2'b11}
The new value of reg1 would be 8'b11001011. 
 
reg1 <= {input_bit,reg1[7:0]};  // reg1 <= {2'b11,8'b10110010}
The new value of reg1 would be 8'b10110010 (unchanged, actually).

Also:

reg1 <= {reg1, input_bit};  // reg1 <= {8'b10110010,2'b11}
The new value of reg1 would be 8'b11001011.

reg1 <= {input_bit,reg1};  // reg1 <= {2'b11,8'b10110010}
The new value of reg1 would be 8'b10110010 (unchanged, actually).