Forum Discussion
humandude
New Contributor
New ContributorSystem Verilog Concatenation
If I have an 8-bit register and I concatenate an input bit to itself excluding the MSB, what does the output look like? My assumption is that the value gets bit-shifted to the left (i.e the MSB gets ...
Yes, 100% correct. Same in Verilog or SystemVerilog.
ak6dn
Regular Contributor
Regular ContributorYes, 100% correct. Same in Verilog or SystemVerilog.
humandudeSo in the case that I use the full register value in my concatenation operation, and add a two-bit value, then the two highest order bits get shifted out (to the left), and so on?
reg [7:0] reg1 = 8'b10110010;
reg input_bit = 2'b11;
reg1 <= {reg1[7:0], input_bit}; // reg1 <= {'b10110010, 'b11}
The new value of reg1 would be 'b11001011.
And from what I understand, the bits would be shifted right instead if I had reversed the order of the operands:
reg1 <= {input_bit,reg1[7:0]}; // reg1 <= {'b11,'b10110010}
The new value of reg1 in this case is 'b11101100.
