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Altera_Forum's avatar
Altera_Forum
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8 years ago

System Verilog 2009 Generate Loop

How can I get this piece of code to compile? This works fine in other synthesis tools, simulation etc. Just trying to map it to an FPGA. In Quartus 17.1 and 18.0 I get this error: Err...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I don't think I've seen the genvar commands inside the loop before. Try putting genvar i and genvar j above the generate keyword. You might also want to try inserting begin/end around the inner for loop. And how and where is N defined?

Also, why are you using generate for simple assignments? Can't you just use a normal for loop?