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LFahem's avatar
LFahem
Icon for Occasional Contributor rankOccasional Contributor
7 years ago
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Synthesis problem when instanciating different GXB tranceivers

Hi, I am making a design that uses Triple Speed Ethernet. My design contains different instances of this IP and I want to define a partition for each TSE instance. However when trying this, Quartus ...
  • LFahem's avatar
    LFahem
    7 years ago

    Hello,

    Apparently, Incremental Compilation can not be done with particular IPs. Actually, hardware IPs like lvds and hps, sould be assigned to the root partition.

    Best regards.

LFahem's avatar
LFahem
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Hi,

Thank you for answering my question. Actually, I made an entity that contains a Triple Speed Ethernet, an FPLL and a Phy Reset Controller. Then I createde a top level design with two instances of this entity. According to th quartus error messages, I think that the problem is coming from the FPLL and the Phy Reset Controller. I have uploaded the bloc design and the quartue error message.

Best regards.