Synthesis output for multiple driver within one always

Re-writing the code with comments might help you understand this ..

always @(posedge clk or posedge rst) begin
  if (rst) begin
    // Reset values    
    a <= 1'b0;
    b <= 1'b1;
  end
  else if (x == 1) begin
    // Defaults
    a <= 1'b0;
    b <= 1'b1;
    // Over-rides
    if (x) begin
       a <= ~a;
    end
    if (~y) begin
      b <= 1;
    end
  end 
end

This style of code can is useful in the combinatorial process of an FSM, as you can ensure that all outputs have assignments.

The synthesis tool infers that the "last assignment" to the output is the winner and generates the combinatorial logic feeding the register accordingly.

Cheers,

Dave