Forum Discussion
bitstreamer
Occasional Contributor
Occasional Contributorsynthesis of synchronous logic in system verilog interfaces
In Quartus, is synchronous processes allowed in system verilog interfaces for synth? I'm seeing messages from quartus indicating that logic signals need an initial value, even when they are assigned ...
SyafieqS
Super Contributor
Super ContributorHi Joe,
You may need to refer to below link for details. I believe system verilog also work as verilog where you need to manually assign value to the net.
bitstreamerOccasional Contributor
Occasional ContributorThat's the problem, it's not working as synthesizable verilog. A register assignment shouldn't be assigned really. Thanks though.
