Forum Discussion
wsiwe
New Contributor
New Contributorsynthesis have a wrong result when some logic in generate block
Quartus version is 16.1 lite and 18.1 lite. As RTL, ror_size_ex is from dsp_…[17:16], when dsp_...[17:16] is 0, , it should be cx_b_dsp_i But see the synthesis result, when dsp_...[17:16] is 0, ...
GuaBin_N_Intel
Contributor
ContributorJust have a glance at the partial code here, I could not get how would you say that "when dsp_...[17:16] is 0". Is that signal "dsp..." is constant value or a variable?
