synthesis have a wrong result when some logic in generate block

Quartus version is 16.1 lite and 18.1 lite. As RTL, ror_size_ex is from dsp_…[17:16], when dsp_...[17:16] is 0, , it should be cx_b_dsp_i But see the synthesis result, when dsp_...[17:16] is 0, ...