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wsiwe's avatar
wsiwe
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6 years ago

synthesis have a wrong result when some logic in generate block

Quartus version is 16.1 lite and 18.1 lite. As RTL, ror_size_ex is from dsp_…[17:16], when dsp_...[17:16] is 0, , it should be cx_b_dsp_i But see the synthesis result, when dsp_...[17:16] is 0, ...
wsiwe's avatar
wsiwe
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6 years ago

thanks for relay. do you mean, I need try to add a large code commented block (100 lines or more) before the generate block and after the generate block?

the commented block may like below:

/*

-------

-------

-------

...

---------

---------

*/

RRomano001's avatar
RRomano001
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6 years ago

hi Wsiwe, yes that what I observed, took some code, not garbage, copy paste then comment out. generally I leave between code I rewrote and at end when change apply'd to new code.

I am trying on Linux took 1 minute to build, when I am sure or close to of what trigger this I can try on other platform.

One time I try'd leave compiling on Win7, same behavior, but appear and disappear in a while.

I am also parallel installing last Ubuntu version to avoid comment from Intel clerks and close the loop to culprit of.

Good answer to this was to change vendor, I am too close to deadline.

My Hardware is intended controlling a mechanical with huge moving part and cannot risk the life of none. This is not a game.

Regards

Robert