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wsiwe
New Contributor
New Contributorsynthesis have a wrong result when some logic in generate block
Quartus version is 16.1 lite and 18.1 lite. As RTL, ror_size_ex is from dsp_…[17:16], when dsp_...[17:16] is 0, , it should be cx_b_dsp_i But see the synthesis result, when dsp_...[17:16] is 0, ...
wsiweNew Contributor
New Contributorthanks for relay. I try to use synplify_pro to generate .qvm, then use the netlist in quartus. but the route can not pass. when I use RTL, quartus route can pass, but when I use netlist, quartus route can not complete. do you have some suggestion about how quartus fit the netlist generated by synplify? thanks.
