PiotrWija
New Contributor
4 years agoSynthesis error while getting parameters from interface
Hi,
I'm trying to synthesis code where based on parameters from interface I create structure and the once again I take interface parameters. Such a case results with error:
Error(13433): Verilog HDL Defparam Statement error at top.sv(34): value for parameter "WIDTH_2" must be constant expression
I check the code in Vivado and Questa and it works well.
Please find attached source code and log from quartus.
Steps to replicate:
- Use `Quartus Prime Pro Edition 22.2.0` with any devices installed
- Create a new project, add following code to `top.sv` file.
- Set `top` as Top-level Entity
- Run `Analysis & Synthesis`
Update from Engineering Team: The issue is planned to fix in the Quartus future release version 23.1.
Thanks.
Best Regards,
Ven Ting