Altera_Forum
Honored Contributor
Honored Contributorsynthese
hello I have a code in vhdl ,I want to do the synthese under quartus can you give me the steps to the synthesis in quartus
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Altera_ForumHonored Contributor
Honored ContributorYou can jump that step, but your FPGA might not work properly if you do.
To create and add an sdc file for timing you will need to read the Timequest chapter 6 and 7 of the QuartusII user manual. http://www.altera.com/literature/hb/qts/qts_qii5v3_02.pdf
