frank..finally i've manage to finish designing my traffic light..thanks for ur advice..but the code is really mess..:p
i'll take my time to clear it..:D
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity allTnew is
port
(clk : in std_logic;
input : buffer std_logic_vector(1 to 4);
g, y, r : out std_logic_vector(1 to 4);
reset : in std_logic);
end entity;
architecture behavT of allTnew is
signal timer : std_logic_vector(3 downto 0);
type state_type is (s1, s2, s4, s5, s7, s8);
signal state : state_type;
begin
process (clk, reset, input)
begin
if reset = '1' then
state <= s1;
input <= "0111";
elsif (clk'event AND clk = '1') then
timer <= (others => '0');
case state is
when s1 =>
if input = "0111" then
g <= "1000";
y <= "0000";
r <= input;
state <= s2;
elsif input = "1011" then
g <= "0100";
state <= s2;
elsif input = "1101" then
g <= "0010";
state <= s2;
elsif input = "1110" then
g <= "0001";
state <= s2;
end if;
when s2 =>
if timer = "0100" then
state <= s4;
g <= "0000";
else
timer <= timer + 1;
end if;
when s4 =>
if input = "0111" then
y <= "1000";
state <= s5;
elsif input = "1011" then
y <= "0100";
state <= s5;
elsif input = "1101" then
y <= "0010";
state <= s5;
elsif input = "1110" then
y <= "0001";
state <= s5;
end if;
when s5 =>
if timer = "0010" then
state <= s7;
y <= "0000";
else
timer <= timer + 1;
end if;
when s7 =>
if input = "0111" then
r <= "1011";
state <= s8;
elsif input = "1011" then
r <= "1101";
state <= s8;
elsif input = "1101" then
r <= "1110";
state <= s8;
elsif input = "1110" then
r <= "0111";
state <= s8;
end if;
when s8 =>
if input = "0111" then
input <= "1011";
state <= s1;
elsif input = "1011" then
input <= "1101";
state <= s1;
elsif input = "1101" then
input <= "1110";
state <= s1;
elsif input = "1110" then
input <= "0111";
state <= s1;
end if;
end case;
end if;
end process;
end behavT;
now its time to make the report for my assigment..:D