Syntax Error

Hello,

basically you have to stop your sequence state machine for a while

case r is 
  when "0111" =>
    r <= "1011";
  when "1011" =>
    r <= "1101";
  when "1101" =>
    r <= "1110";
  when "1110" =>
    r <= "0111";
  when others =>
   null;
end case;

I would embed the delay counter directly to the state maschine, but that's a matter of taste.

CASE state IS
WHEN S1 =>
  timer <= conv_unsigned(10,4);
WHEN S_WAIT =>
  IF timer = 0 THEN
    state <= S_UP;
  ELSE
    timer <= timer - 1;
  END IF;
WHEN S_UP =>

Basically I would use named states rather than defining state variable coding myself. Did you notice, that Quartus has a template function in HDL editor context menu? It also includes FSM examples with usual VHDL syntax.

Regards,

Frank