Honored Contributor
Honored ContributorA .qip file often compiles IP into different libraries. For example, if you create two DDR3 interfaces, they may both have a file called calibration.v(I'm making that up as an example). Now, in Verilog and VHDL you can't add two files with the same top level name. (They may be identical, but synthesis doesn't know that and doesn't check for it). Normally you would only add it once, but that would be a pain with IP, having to manage which files are duplicates from other IP and selectively removing them. The way it's handled is the .qip compiles them into libraries that match the IP name, so for example, you can have two distinct calibration.v files.
I'm guessing Synplify reads them in, but when it writes them into the .vqm it removes that separation. If you search the .vqm, are there more than one module with that name? There are probably multiple ways to solve this, but I think the easiest would be to let Quartus synthesize the IP and just black-box it in Synplify.
