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Altera_Forum's avatar
Altera_Forum
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11 years ago

Syncronous counter generating rippled outputs

This thing is driving me crazy. I have been trying to make a synchronous 16 bit divide-by-N counter with schematic entry. I got the logical part working. Two different designs. Both seem to be co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Without sdc file for timing constraints the tool defaults to that funny speed.

You must add sdc file to determine your clock name and speed. And you also need to determine io constraints.

Additionally for io use fast output registers.