Synchronization on falling and rising edges

Hello, please How to my code takes 756 total logic elements. Can I somehow save the data to an external RAM or internal RAM . How?

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity Number_converter is

port( INPUT12bit: in unsigned (11 downto 0);

digit1: out unsigned (11 downto 0);

digit2: out unsigned (11 downto 0);

digit3: out unsigned (11 downto 0);

digit4: out unsigned (11 downto 0));

end entity;

architecture main of Number_converter is

signal INPUT12bit_INT:integer range 0 to 4096;

attribute ramstyle: string;

attribute ramstyle of digit4 : signal is "M9K";

begin

digit1<=(INPUT12bit rem 10)/1;

digit2<=(INPUT12bit rem 100)/10;

digit3<=(INPUT12bit rem 1000)/100;

digit4<=(INPUT12bit/1000);

end main;