Synchronization on falling and rising edges

OK problem resolved!

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity encoder is

port( clk:in std_logic;

state_A:in std_logic;

B:in std_logic;

number:buffer unsigned(11 downto 0):=(others=>'0'));

end encoder;

architecture main of encoder is

signal number1:unsigned (11 downto 0):=(others=>'0');

signal number2:unsigned (11 downto 0):=(others=>'0');

signal cislo:unsigned (11 downto 0):=(others=>'0');

signal NOTstate_A: std_logic;

begin

ld:process(state_A,NOTstate_A)

begin

if rising_edge(state_A) then

if B='0' then

number1<=number1 + 1;

end if;

if B='1' then

number1<=number1 - 1;

end if;

end if;

if rising_edge(NOTstate_A) then

if B='1' then

number2<=number2 + 1;

end if;

if B='0' then

number2<=number2 - 1;

end if;

end if;

end process;

NOTstate_A<=not state_A;

cislo<=number1+number2;

number<=not cislo;

end main;