Synchronization on falling and rising edges

Hello Tomsik,

I had a similar problem some time ago.

The trick i used is to generate the flank detections on an internal FPGA clock.

This clock is normally a lot faster than the ecoder timing, so it should not be a problem.

wire a;

wire b;

assign a = KEY[0];

assign b = KEY[1];

reg aPrev;

reg bPrev;

always @(posedge CLOCK_50)

begin

// mounting flank on A

if (a > aPrev)

begin

if (b==0)

r <= r+1;

else

r <= r-1;

end

// descending flank on a

if (a < aPrev)

begin

if (b==1)

r <= r + 1;

else

r <= r - 1;

end

aPrev<=a;

bPrev<=b;

end

Best Regards,

Johi.