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Altera_Forum
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16 years ago

Synch Counter Problems

I am new at altera and using Quartus II v 9.0.. I am using the block editor to create a simple circuit with a synchronous counter (MAX7000S Family). Used the megawizard and configured it to count down with a synchronous set capability. When I couple the Cout back into the SSet it causes the Cout of the counter to oscillate during the Carry out period as viewed in the simulator. If I don't couple it to the SSet it responds as I would expect. I looked at the counter equivalent logic diagram and could see no reason why applying the cout to the sset should cause any oscillations since the outputs of the counter are not changing until the clock edge. The oscillation period is approximately 20nsec. Any thoughts

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  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I also see irregular waveforms in CPLD simulation (MAX7000 and MAX3000) with Quartus timing simulation. I think, it's a simulator artefact. Because the respective signal is sourced from a single DFFE with only CLK and D inputs connected, the real signal can't look like the simulation shows up.

    P.S: When choosing a FPGA like MAX II, COUT is using combinational logic acrosse several LEs, so it has some small glitches, but not like the strange artefacts in MAX7000 simulation.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Does that mean that the design will work and just the simulation is effected??

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Yes, that's my assumption. I can't exclude a synthesis error with MAX7000, too. But in the observed cases, the synthesis result seems to be correct. I remember, that I once had MAX7000 synthesis errors with combinational circuits in old MAXPlus, but they have been obvious in physical mapping and timing simulation as well.