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Altera_Forum
Honored Contributor
8 years ago[SVA] signal rise and stay stable -> how to write an assertion?
Hi All, How can I write an assertion for a signal, which should rise within between 10 to 20 cycles and stay stable (HIGH) until the assertion will be disabled? Thank you!
Altera_Forum
Honored Contributor
8 years agoThanks for sharing your thoughts!
BTW, what's the difference between the# #1:3a and a[1:3] syntax?