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Altera_Forum's avatar
Altera_Forum
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7 years ago

[SVA] signal rise and stay stable -> how to write an assertion?

Hi All, How can I write an assertion for a signal, which should rise within between 10 to 20 cycles and stay stable (HIGH) until the assertion will be disabled? Thank you!
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

"SVA is also something very few FPGA engineers will be using" - why? FPGA engineers still need to write TestBench... it should be much easier to write assertions than going to waveform each time and check behavior of all the signals there...