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Altera_Forum's avatar
Altera_Forum
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9 years ago

[SV] How does Quartus decide when to use registers? (after analyses and synthesis)

Hi everybody!

I have the following concern: I have a module with a single 5-bit variable defined as logic which I use inside an always_ff which increases it every clock cycle.

My question is: when I run the analyses and synthesis, why the number of registers (in the flow summary) is zero? When is it supposed to increase?

I thought a register would be a single 1-bit flip-flop, but it seems is not. I also couldn't find better information about these registers in the datasheet of my FPGA (cyclone iv e EP4CE115F29C7)

thank you if you can help me!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Have you connected the outputs from your design to some pins on the FPGA? without connecting it to the output, you will get no logic.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Nope, but in another design I didn't do it as well but in the flow summary it says that some registers were used. But the strange thing is the amount of them that is not right.

    Here is the second one that takes 41 registers (please disregard the meaning of the code itself) 

    module seq_mul_add_2(
	input logic clock, reset,
	input logic  X1, X2, Y,
	output logic  Zo,
	output logic data_is_ready
);
logic  Z;
logic  k,l,m;
always_ff @ (posedge clock) begin
	if( reset ) begin
		data_is_ready <= 0;
		k <= 0;
		l <= 0;
		m <= 0;
		Z <= 0;
		Zo <= 0;
	end else begin
		l++;
			
		if( l<=13 ) begin
			Z <= Z + X1 * X2;
		end
		
		if( l==14 ) begin
			l <= 0;
			Z <= 0;
			m++;
			data_is_ready <= 1;
			Zo <= Z + Y;
		end else
			data_is_ready <= 0;
		
		if( m==13 ) begin
			m <= 0;
			k++;
		end
	end
end
endmodule