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vraj12's avatar
vraj12
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4 years ago

SV assertions not honored?

i have a simple sv code, which has assertions module top(input [2:0] in1, input [2:0] in2, output [3:0] out1, input clk); parameter p1 = 4; parameter p2 = 5; reg [3:0] out1_reg; always @(posedg...
sstrell's avatar
sstrell
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4 years ago

What are you expecting? assert is used for simulation, not synthesis.

vraj12's avatar
vraj12
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4 years ago

In the snippet it is mentioned as supported and it does not say ignored by synthesis, was expecting it prints out the message in log.

Immediate assertion is similar to if statements, so was expecting some logic is generated