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Honored Contributor
Honored ContributorStuck clock
Hi all, I'm trying to build a microprogrammed computer, but get problems
when I try to implement the bus. "Warning (14110): No clock transition on "sram:SRAM1|addr_reg[0]" register due to stuck clock or clock enable" I get several of these, but they disappear if I comment out the last line with the assignment to sram_address. Have I made an error?library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity sram is
port(reset, clk : in std_logic;
sram_address : out std_logic_vector(17 downto 0);
sram_data : inout std_logic_vector(15 downto 0);
sram_ub_n, sram_lb_n, sram_ce_n : out std_logic;
bus_line : inout std_logic_vector(15 downto 0);
addr_r, dq_r, dq_w : in std_logic
);
end sram;
architecture arch of sram is
signal addr_reg : std_logic_vector(15 downto 0);
begin
process(clk, reset)
begin
if reset = '0' then
addr_reg <= (others => '0');
elsif rising_edge(clk) and addr_r = '1' then
addr_reg <= bus_line;
end if;
end process;
bus_line <= sram_data when dq_w = '1' else (others => 'Z');
sram_data <= bus_line when dq_r = '1' else (others => 'Z');
sram_ub_n <= '0';
sram_lb_n <= '0';
sram_ce_n <= '0';
sram_address(17 downto 16) <= (others => '0');
sram_address(15 downto 0) <= addr_reg;
end arch;
