Stratix IV GX - ALTPLL in VHDL

Hi!

Devide used: Stratix IV, EP4SGX180KF40C02N

Software used: Quartus II, 13.0.1.232; also tried compiling with v12 and v9.

I am trying to get a simple PLL frequency multiplier running in VHDL using the megafunction "altpll", which generates 320MHz out of 40MHz:

--------------------------------------------------------- Begin of Code

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

library altera_mf;

use altera_mf.altera_mf_components.all;

entity test_stratix_pll is

port (

clk0_in : in std_logic -- 40MHz

);

end;

architecture BEHAVIOR of test_stratix_pll is

signal clock : std_logic := '0'; -- 40MHz

signal highspeed_serial_tx_clock_320MHz : std_logic := '0';

signal highspeed_serial_tx_clock_320MHz_all : std_logic_vector (9 downto 0);

begin

Clock <= clk0_in;

highspeed_serial_tx_clock_320MHz_generator : altpll -- generates 320MHz from the 40MHz-Clock.

generic map (

intended_device_family => "Stratix IV",

clk0_multiply_by => 8,

clk0_divide_by => 1,

inclk0_input_frequency => 25000,

inclk1_input_frequency => 25000,

operation_mode => "normal",

width_clock => 10

)

port map (

--clk(0) => highspeed_serial_tx_clock_320MHz,

clk => highspeed_serial_tx_clock_320MHz_all,

inclk(0) => clock,

inclk(1) => clock

);

end BEHAVIOR;

----------------------------------------------------------- End of Code

With a Cyclone II using the following code for the altpll in the otherwise identical VHDL it worked immediately as intended, verified per oscilloscope:

--------------------------------------------------------- Begin of Code

highspeed_serial_tx_clock_320MHz_generator : altpll -- generates 320MHz from the 40MHz-Clock.

generic map (

clk0_multiply_by => 8,

clk0_divide_by => 1,

inclk0_input_frequency => 25000,

inclk1_input_frequency => 25000,

operation_mode => "normal"

)

port map (

clk(0) => highspeed_serial_tx_clock_320MHz,

inclk(0) => clock

);

----------------------------------------------------------- End of Code

But with the Stratix i get the huge list of error messages shown at the attached file quartus-error-messages.txt ...

I also tried all the parameters the MegaWizard gave me, and most of these described in the altpll-documentation, and a lot of variations of it (i spent about 2 days with it....), with or without reset lines and so - no change... for example:

--------------------------------------------------------- Begin of Code

GENERIC MAP (

bandwidth_type => "AUTO", clk0_divide_by => 1, clk0_duty_cycle => 50, clk0_multiply_by => 8, clk0_phase_shift => "0", compensate_clock => "CLK0", inclk0_input_frequency => 25000,

intended_device_family => "Stratix IV", lpm_hint => "CBX_MODULE_PREFIX=bla", lpm_type => "altpll", operation_mode => "NORMAL", pll_type => "AUTO", port_activeclock => "PORT_UNUSED",

port_areset => "PORT_USED", port_clkbad0 => "PORT_UNUSED", port_clkbad1 => "PORT_UNUSED", port_clkloss => "PORT_UNUSED", port_clkswitch => "PORT_UNUSED", port_configupdate => "PORT_UNUSED",

port_fbin => "PORT_UNUSED", port_fbout => "PORT_UNUSED", port_inclk0 => "PORT_USED", port_inclk1 => "PORT_UNUSED", port_locked => "PORT_UNUSED", port_pfdena => "PORT_UNUSED",

port_phasecounterselect => "PORT_UNUSED", port_phasedone => "PORT_UNUSED", port_phasestep => "PORT_UNUSED", port_phaseupdown => "PORT_UNUSED", port_pllena => "PORT_UNUSED",

port_scanaclr => "PORT_UNUSED", port_scanclk => "PORT_UNUSED", port_scanclkena => "PORT_UNUSED", port_scandata => "PORT_UNUSED", port_scandataout => "PORT_UNUSED", port_scandone => "PORT_UNUSED",

port_scanread => "PORT_UNUSED", port_scanwrite => "PORT_UNUSED", port_clk0 => "PORT_USED", port_clk1 => "PORT_UNUSED", port_clk2 => "PORT_UNUSED", port_clk3 => "PORT_UNUSED", port_clk4 => "PORT_UNUSED",

port_clk5 => "PORT_UNUSED", port_clk6 => "PORT_UNUSED", port_clk7 => "PORT_UNUSED", port_clk8 => "PORT_UNUSED", port_clk9 => "PORT_UNUSED", port_clkena0 => "PORT_UNUSED", port_clkena1 => "PORT_UNUSED",

port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED", port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED", using_fbmimicbidir_port => "OFF", width_clock => 10

)

----------------------------------------------------------- End of Code

I would be very grateful for any hint what i can do to get the PLL running.

Thanks in advance, best regards :-)