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I usually instantiate RAMs and FIFOs directly, without using the MegaWizard. (hence my setting of 5 ...)
Now 8192 words of 9 bits is definitely larger than 8 (or 36).
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Yes, sorry for misunderstanding before.
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Is 'aclr' connected and in which clock domain is it generated?
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Yes it is, I've enabled sync to wrclk, which is actually coming from that clock. 135MHz clock is used by ASI megacore, so the data and status signals should be already synchronous to that clock. I am using cable-sync signal (when core detects connected cable, status signal goes high) as reset source to the FIFO. This means, that when the cable is not connected, fifo is in reset condition. I am not sure if core generates sync chains inside for this cable-sync-loss signal, so I've enabled synchronizer there. On the other hand, I've tried to disable it with no success. Maybe I should remove clear signal at all for some tests?
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The output stream looks like 3 writes with '0x00' have preceded the '0x47' one. After that the stream is correct.
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I am triggering on the start signal and my signaltap memory is quite short. According to the results I observe, I believe I get such data corruptions every received packet (packet length = 188 bytes).
Altera says that I should wait a few cycles after reset before asserting wrreq. Maybe this could be an issue?
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