Stratix III FPGA: Problem using Asynchronous FIFOs

It's 9bit on write side and 36bit on read side:

component ts_fifo1
PORT (
        aclr        : IN STD_LOGIC := '0';
        data        : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
        rdclk        : IN STD_LOGIC;
        rdreq        : IN STD_LOGIC;
        wrclk        : IN STD_LOGIC;
        wrreq        : IN STD_LOGIC;
        q            : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
        rdempty    : OUT STD_LOGIC;
        rdusedw    : OUT STD_LOGIC_VECTOR(10 DOWNTO 0));
end component;

PARAMETERS
(
    ACF_DISABLE_MLAB_RAM_USE = "FALSE",
    ADD_RAM_OUTPUT_REGISTER = "OFF",
    ADD_USEDW_MSB_BIT = "OFF",
    CLOCKS_ARE_SYNCHRONIZED = "FALSE",
    DELAY_RDUSEDW = 1,
    DELAY_WRUSEDW = 1,
    LPM_NUMWORDS,
    LPM_SHOWAHEAD = "OFF",
    LPM_WIDTH,
    LPM_WIDTH_R = 0,
    LPM_WIDTHU = 1,
    LPM_WIDTHU_R = 1,
    MAXIMIZE_SPEED = 5,
    OVERFLOW_CHECKING = "ON",
    RAM_BLOCK_TYPE = "AUTO",
    RDSYNC_DELAYPIPE = 5,
    READ_ACLR_SYNCH = "OFF",
    UNDERFLOW_CHECKING = "ON",
    USE_EAB = "ON",
    WRITE_ACLR_SYNCH = "OFF",
    WRSYNC_DELAYPIPE = 5,
    CBXI_PARAMETER = "NOTHING"
);