Stratix III FPGA: Problem using Asynchronous FIFOs

Hello,

I've also got interesting problem with DCFIFO, which is mixed width.

The FIFO has 9bit input (start signal plus 8bit data) and 36bit output. Input clock: 135MHz, but wrreq is asserted only every 5 clock edges, so basically I have a 27MHz data flow. The read side use 125MHz clock and starts reading the data when the FIFO is half full (I use rdusedw bus for that). Pipeline level set to 3.

The problem is that on signaltap, I see incoming data:

0x47 0x1F 0xFF 0x10 0x00 0x00 0x00 0x00

But the output is a mess:

0x47000000 0x0010FF1F

Strange is that I can rarely get the design working correctly, but mostly this part fails. I suppose, I have some timing problems, so let's check what do I have.

In order to see timing errors between clock crossings, I've made async clock groups:

set_clock_groups -asynchronous 
                  -group { 
                  PLL0|altpll_component|auto_generated|pll1|clk 
                  PLL0|altpll_component|auto_generated|pll1|clk 
                  } 
                  -group { 
                  PLL1|altpll_component|auto_generated|pll1|clk 
                  PLL1|altpll_component|auto_generated|pll1|clk 
                  PLL1|altpll_component|auto_generated|pll1|clk 
                  }#  Here:#  PLL0 c0 -> 125MHz system clock (runs QSys and all the stuff)#  PLL0 c1 -> 125MHz -65deg clock, which goes directly to SDRAM chip clk pin#  PLL1 c0 -> 337.5MHz ASI soft receiver oversample clock#  PLL1 c1 -> 337.5MHz +90deg same as above#  PLL1 c2 -> 135MHz ASI receiver data clock

The timequest shows me some setup violations, but that are only for Qsys internal signals, which has nothing to do with the FIFO I'm writing here, so I am not sure what's happening. Is it possible to see Fmax for FIFO interfaces? Or maybe my read clock is too fast?

Thanks.