Honored Contributor
Honored ContributorIt's not possible to perform timing analysis on unrelated clocks because.. they're unrelated: they may drift, they may have unknown phase relations.
Static timing analysis needs to know the timing of the edges of the clocks in respect to one another. Case 1: consider CLK1 and CLK2 which are generared from 2 different 10 MHz crystals. Since the crystals are never perfect, one may be 10.00001 MHz while the other may be 9.999999 MHz. This means the clock edges will drift one in relation to another. You can't do timing analysis on transfers between these two clocks. Case 2: consider CLK1 and CLK2 which are generated from the same crystal but because CLK2 passes through a unknown length of cable and thus you can't know the phase of CLK1 in relation to CLK2. Again, you can't do timing analysis on transfers between these two clocks. Case 3: consider CLK1 and CLK2 which are generated from the same crystal, and go through some propagation chain BUT in this case you know the phase of CLK1 in respect to CLK2 at the FPGA's input pins, with a small error. Now you have two related clocks and transfers between these two clocks can be analysed -- you can use a set_clock_uncertainty constraint to handle the error. In this situation, you should go with option "A". If you do have unrelated clocks, then your only option for a gate level simulation is to disable timing checks on the synchronization registers.
