Honored Contributor
Honored ContributorThere are seven timing violations. This events are produced by both FIFOs. I can attach some parts of the log where you can see the events
SETUP Low VIOLATION ON aclr WITH RESPECT TO clk; /tb_fifo/UUT/\fifo_cmp|dcfifo_component|auto_generated|fifo_ram|ram_block9a108\/addr_b_register SETUP Low VIOLATION ON aclr WITH RESPECT TO clk; /tb_fifo/UUT/\fifo_cmp|dcfifo_component|auto_generated|fifo_ram|ram_block9a72\/addr_b_register SETUP Low VIOLATION ON aclr WITH RESPECT TO clk; /tb_fifo/UUT/\fifo_cmp|dcfifo_component|auto_generated|fifo_ram|ram_block9a0\/addr_b_register SETUP Low VIOLATION ON aclr WITH RESPECT TO clk; /tb_fifo/UUT/\fifo_cmp|dcfifo_component|auto_generated|fifo_ram|ram_block9a36\/addr_b_register HOLD High VIOLATION ON DATAIN WITH RESPECT TO CLK /tb_fifo/UUT/\fifo_cmp|dcfifo_component|auto_generated|rs_dgwp|dffpipe10|dffe11a[1] SETUP High VIOLATION ON ASDATA WITH RESPECT TO CLK; /tb_fifo/UUT/\fifo2_cmp|dcfifo_component|auto_generated|ws_dgrp|dffpipe14|dffe15a[0] SETUP High VIOLATION ON ASDATA WITH RESPECT TO CLK; /tb_fifo/UUT/\fifo2_cmp|dcfifo_component|auto_generated|ws_dgrp|dffpipe14|dffe15a[3]
