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I get those frequencies using TimeQuest Analyser from Quartus, but when I try to test my design using modelsim (with the .vho and .sdo files) it doesn't work for those frequencies. So, can the frequencies be wrong?
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No the frequencies are correct. But you need to carefully generate your input signals, i.o.w. they must respect proper setup times as reported byt the Datasheet Report in TimeQuest.
Now I try to avoid Gate Level Simulation in Timequest. A: because of the input setup requirements, the output delays. B: you can not probe every signal as the ones optimized away are niot there anymore. Furthermore the ones you can watched are 'real time' and are shifted in regards with the input clocks, so if you are debugging a design it gets difficult to see cause and action. And C: it is painfully slow compared to RTL simulation. Of course if you are designa a physical module like a Memory PHY you utlimnately have to run Gate Level Simulation, although TimeQuest can tell you all about it.
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Referring to the sdc file, how can I set the output delays?
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You could read Rysc's Timequest doc, you can find it on the wiki:timequest user guide (
http://www.alterawiki.com/wiki/timequest_user_guide)
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