Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Stratix-4 DDR3 dqs_n fitter error

Hi All,

I am using a Stratix-4 Dev. board and am trying to add a DDR3 UniPHY controller. All is fine until I get to the fitter which gives me the error:

error (176718): pin memory_mem_dqs_n[0] uses pseudo-differential output node rootport_fifo_qsys:u0|rootport_fifo_qsys_mem_if_ddr3_emif_0:mem_if_ddr3_emif_0|rootport_fifo_qsys_mem_if_ddr3_emif_0_p0:p0|rootport_fifo_qsys_mem_if_ddr3_emif_0_p0_memphy:umemphy|rootport_fifo_qsys_mem_if_ddr3_emif_0_p0_new_io_pads:uio_pads|rootport_fifo_qsys_mem_if_ddr3_emif_0_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|pseudo_diffa_0. however, these pins also have an i/o standard lvds that cannot be supported by the pseudo-differential output node.

I just can't understand this, Quartus generates the pinout automatically, right ? I have no control over the process other than tell it the type of memory hooked up to the controller. The pins are fixed by the PCB in advance. How does Quartus know which Dev. board pinout to assign the pins to? And then it generates the wrong pinout and gives me an error:mad:

Can someone enlighten me? Help me please !:oops:

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Dear arisrama22,

    Do not make any assignment or add any pins before you make a 'analysis and synthesis' for you design then make a whole compilation after that should not have any problems.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Hello, I have the same problem: after running the *pin_assignment.tcl, in pin planner are false differential pins *_ck[0](n) instead of *_ck_n[0] etc. Did somebody found the solution?

    --- Quote End ---

    I have solved my problem. I had to make the following steps:

    1. Generate the Qsys project

    2. Run Analysis&Synthesis

    3. Run the *_pin_assignments.tlc Script (the Pins will be wrong still wrong at this place), 4. Remove incremental_db

    5. Make the full compilation of the project

    As a result all pins will be correct and I could fit my design.