Altera_Forum
Honored Contributor
13 years agoStratix-4 DDR3 dqs_n fitter error
Hi All,
I am using a Stratix-4 Dev. board and am trying to add a DDR3 UniPHY controller. All is fine until I get to the fitter which gives me the error: error (176718): pin memory_mem_dqs_n[0] uses pseudo-differential output node rootport_fifo_qsys:u0|rootport_fifo_qsys_mem_if_ddr3_emif_0:mem_if_ddr3_emif_0|rootport_fifo_qsys_mem_if_ddr3_emif_0_p0:p0|rootport_fifo_qsys_mem_if_ddr3_emif_0_p0_memphy:umemphy|rootport_fifo_qsys_mem_if_ddr3_emif_0_p0_new_io_pads:uio_pads|rootport_fifo_qsys_mem_if_ddr3_emif_0_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|pseudo_diffa_0. however, these pins also have an i/o standard lvds that cannot be supported by the pseudo-differential output node. I just can't understand this, Quartus generates the pinout automatically, right ? I have no control over the process other than tell it the type of memory hooked up to the controller. The pins are fixed by the PCB in advance. How does Quartus know which Dev. board pinout to assign the pins to? And then it generates the wrong pinout and gives me an error:mad: Can someone enlighten me? Help me please !:oops: