stop inferred RAM

I hope someone can help, I am not too familiar with verilog and and trying to edit and SOPC component to stop it using M4K blocks and instead use registers.

module raminfr   
        (clk, we, a, dpra, di, dpo); 
parameter addr_width = 4;
parameter data_width = 8;
parameter depth = 16;
input clk;   
input we;   
input   a;   
input   dpra;   
input   di;   
output  dpo;   
reg     ram ; 
wire  dpo;
wire   di;   
wire   a;   
wire   dpra;   
 
  always @(posedge clk) begin   
    if (we)   
      ram <= di;   
  end   
  assign dpo = ram;   
endmodule