Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

STD_LOGIC_VECTOR error

I'm trying to implement following verilog peace of code in vhdl reg [11:-2]center; it's clear center is an 14 bit register. but in vhdl signal center : std_logic_vector(11 downto -...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

--- Quote Start ---

thank you for the quick reply sir,

what if i used following code instead using std_logic_vector

signal center: integer range 0 to 16384 -- (13 downto 0)

will it be the same ?

--- Quote End ---

Almost, I think you mean:

signal center : integer range 0 to 16383;

As this is 14 bits. 16384 requires 15 bits.

But you still have the same problem as I outlined above - you need to offset everything else, not just the center signal.