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Altera_Forum
Honored Contributor
Honored ContributorSTD_LOGIC_VECTOR error
I'm trying to implement following verilog peace of code in vhdl reg [11:-2]center; it's clear center is an 14 bit register. but in vhdl signal center : std_logic_vector(11 downto -...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- i'm trying to design a game using vhdl. an original source for this game was found in verilog. in that they used this negative indexing inside reg. i tried to chnage the reg indexing as reg[13:0] and game did'nt worked. original verilog code as follows --- Quote End --- Did you also offset all of the constants and additions and assignments that take place on center? everything needs to be left shifted by 2.
