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Altera_Forum
Honored Contributor
Honored ContributorSTD_LOGIC_VECTOR error
I'm trying to implement following verilog peace of code in vhdl reg [11:-2]center; it's clear center is an 14 bit register. but in vhdl signal center : std_logic_vector(11 downto -...
Altera_ForumHonored Contributor
Honored ContributorHi,
Why do you need negative index? Write more details what your code does with "center" signal.
