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Altera_Forum
Honored Contributor
Honored ContributorSTD_LOGIC_VECTOR error
I'm trying to implement following verilog peace of code in vhdl reg [11:-2]center; it's clear center is an 14 bit register. but in vhdl signal center : std_logic_vector(11 downto -...
Altera_ForumHonored Contributor
Honored Contributorthank you for the quick reply sir,
what if i used following code instead using std_logic_vector signal center: integer range 0 to 16384 -- (13 downto 0) will it be the same ?
