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Altera_Forum
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9 years ago

STD_LOGIC_VECTOR error

I'm trying to implement following verilog peace of code in vhdl reg [11:-2]center; it's clear center is an 14 bit register. but in vhdl signal center : std_logic_vector(11 downto -...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

use

std_logic_vector(13 downto 0) and offset everything by 2.

Not really any other way around it for std_logic_vector.

Why has the value got -ve indices? is it a fixed point value. The fixed point types allow negative ranges as they provide bit that represent numbers that are 2^N (ie. -ve indeces are to the RHS of a decimal point:

signal centre : ufixed(11 downto -2);