Forum Discussion
Tim10
New Contributor
New ContributorState Machine Wizard
I used the State Machine Wizard to create a machine with 9 states. Looking through the generated code I saw this: reg [8:0] fstate;
reg [8:0] reg_fstate;
parameter State1=0,State2=1,State3=2,State4...
JOHI
Contributor
ContributorHello Tim10,
If implemented in fpga fabric, it is much more efficient to use the bit-by-bit approach compared to a counter approach.
So the total amount of space used is less. An FPGA does not have an ALU as a microprocessor does have.
Best regards,
Johi
Tim10New Contributor
New ContributorHi Johi,
That's a good point, but the wizard has generated 9-bit registers for one-hot encoding, yet generated state parameters using binary encoding, which is inconsistent.
From reading Efficient State Machine Design it seems that the actual encoding and therefore the size of the registers are determined at a later stage in the design flow, so the wizard's inconsistency at the initial Verilog stage seems irrelevant.
Thanks,
Tim.
