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Altera_Forum
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7 years ago

State Machine Viewer - missing transition

Hello every one, can you explain me why I get different state transition diagram from relatively the same VHDL? Here is the code: 1) if rx_bit_in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Hi Vikas,

not realy.

may be I didn't explained correctly the case.

The both IFs are with in a clocked process within a case. The IFs are just the transition condition to the next state, and they are equivalent: when 7 -> transition else count. I can describe as count if < 7 else transition or count and if = 7 transition.

In the simulation it is corect in real test too but the state machine viewer do not like the "<" sign :)

Regards,

Emil