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Altera_Forum
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11 years ago

State machine unstable

Hi, I'm sort of new to Verilog (only used it for a few months) but I have worked with HW and SW design for a long time. Verilog seemed fun and I went ahead to try it on a cool project. htt...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi Jonase,

As you mention "It says it can run my design at 115MHz, and I run at 100MHz, so it should be ok. I'm using about 50% of the gates and 90% of the RAM". Is really a timing issue, are you able to do some timing analysis, and confirm which path have a longest path that fail setup and hold time.