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Altera_Forum
Honored Contributor
Honored ContributorState machine unstable
Hi, I'm sort of new to Verilog (only used it for a few months) but I have worked with HW and SW design for a long time. Verilog seemed fun and I went ahead to try it on a cool project. htt...
Altera_ForumHonored Contributor
Honored ContributorThis sounds very much like a timing problem or problem with asynchronous logic somewhere. Do you have proper timing specs? Do you have some logic that is not synchronised to the system clock.
If you have asynchronous logic you are luck to get the fitter to give you a placement that doesnt violate some timing relationship. The seed value for the fitter changes on every change on source code (ANY chance completly changes the seed) or fitter seed (set via the project settings). Are all signals synchronous to the main clock? are there any paths that you havent synchronised?
