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Altera_Forum
Honored Contributor
Honored ContributorState machine unstable
Hi, I'm sort of new to Verilog (only used it for a few months) but I have worked with HW and SW design for a long time. Verilog seemed fun and I went ahead to try it on a cool project. htt...
Altera_ForumHonored Contributor
Honored Contributorhi,
my experience is that state machines get unstable if controlling Input signals are not synchronized with FSM clock... Maybe you are facing similar effects?
