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Altera_Forum
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17 years ago

State machine transitioning into illegal state

I am working with a simple state machine with 4 states. The state machine is properly detected by Altera's state machine optimizer, and the state diagram it produces is correct. When I probe t...
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Altera_Forum
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17 years ago

Problem fixed.

It turns out that not registering/synchronizing signals across clock domains was indeed the problem, and in more than one location. In one FSM I was only single registering the input, and in another I was reading the count from the wrong side of a DCFIFO.

Lesson learned: Be very vigorous about following proper clock domain crossing boundaries and follow Altera's recommendations as laid out in Application Note 473.