State machine transitioning into illegal state

I didn't read all the posts, but one-hot state-machines will have an all 0s state when looked at in SignalTap or in a timing simulation. The reason is that the registers power up to all 0s. In your state-diagram, the idle state is shown as being all 0s. In essence, it's just like a normal one-hot except the lsb is inverted:

0000

0011

0101

1001

Synthesis still decodes off a single bit, but for the idle state we just decode if the LSB is a 0 instead of if it's a 1.

Also, if bringing asynchronous signals into a SM, I would recommend double-registering them in the new domain to shake out metastability.