State machine transitioning into illegal state

Register the state machine outputs if you can. You might need to assert them one state early to compensate for the additional latency of the output registers.

If the state machine outputs are combinational, they will not glitch if their logic has at most one input toggling at a time. If the state code bits are the only inputs to the logic for state machine outputs, then Gray encoding will avoid glitches. 1-hot will have 2 bits toggling at each state change, which can cause a glitch on any LUT fed by both of those bits.