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Altera_Forum
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17 years ago

State machine transitioning into illegal state

I am working with a simple state machine with 4 states. The state machine is properly detected by Altera's state machine optimizer, and the state diagram it produces is correct. When I probe t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I see - you are correct, the sensitivity list for all state machines and registers is 

always @(posedge Clk, negedge Rst_)

Do you know what would be required to prevent glitches in the state machine outputs? Would forcing the state machine into 1-hot or Gray encoding guarantee this?